banco de pruebas detector de secuencias 1101

library ieee;
use IEEE.STD_LOGIC_1164.all;
entity bp_detector_secuencia is
end bp_detector_secuencia;
architecture estructural of bp_detector_secuencia is
    signal  bp_RESET, bp_RELOJ, bp_X, bp_Z : std_logic;
begin
uut: entity work.det_sec(detector_1)
port map ( RESET=>bp_RESET, CLK=>bp_RELOJ, x=>bp_X );
             process
      begin
         bp_RESET <= '1';     -- inicializa al sistema
                     bp_RELOJ <= '0';
                     bp_X <= '0';
                     wait for 50 ns;
                     bp_RESET <= '0';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '0';
                     bp_X <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <='0';
                     bp_X <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '0';
                     bp_X <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '0';
                     bp_X <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <='0';
                     bp_X <= '0';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '0';
                     bp_X <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '0';
                     bp_X <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <='0';
                     bp_X <= '0';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '0';
                     bp_X <= '0';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '0';
                     bp_X <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <='0';
                     bp_X <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '0';
                     bp_X <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '0';
                     bp_X <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <='0';
                     bp_X <= '0';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '0';
                     bp_X <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '0';
                     bp_X <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <='0';
                     bp_X <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '0';
                     bp_X <= '0';
                     wait for 50 ns;
                     bp_RELOJ <= '1';
                     wait for 50 ns;
                     bp_RELOJ <= '0';
                     bp_X <= '1';
                     wait for 50 ns;
    end process;
end architecture estructural;