aqui les dejo el codigo en VHDL para un decodificador 3 a 8 utilizando process, case, if y vectores. Les recomiendo Geany para escribir el codigo y ModelSim para compilarlo y probarlo. exito
library ieee;
use ieee.std_logic_1164.all;
entity decodificador_3_a_8 is
port ( H : in std_logic;
S : in std_logic_vector(2 downto 0);
D : out std_logic_vector(7 downto 0));
end decodificador_3_a_8;
architecture estructural_1 of decodificador_3_a_8 is
begin
process(S,H)
begin
case s is
when "000" =>
if H ='1' then
D <= "00000001";
else
D <= "00000000";
end if;
when "001" =>
if H ='1' then
D <= "00000010";
else
D <= "00000000";
end if;
when "010" =>
if H ='1' then
D <= "00000100";
else
D <= "00000000";
end if;
when "011" =>
if H ='1' then
D <= "00001000";
else
D <= "00000000";
end if;
when "100" =>
if H ='1' then
D <= "00010000";
else
D <= "00000000";
end if;
when "101" =>
if H ='1' then
D <= "00100000";
else
D <= "00000000";
end if;
when "110" =>
if H ='1' then
D <= "01000000";
else
D <= "00000000";
end if;
when "111" =>
if H ='1' then
D <= "10000000";
else
D <= "00000000";
end if;
when others =>
D <= "00000000";
end case;
end process;
end estructural_1;
listo.
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